Tone generator for generating selected frequencies

ABSTRACT

A tone generator comprising a pulse oscillator, a divider having an adjustable integer dividend which is connected thereto and which comprises a sub-divider having an adjustable fractional dividend, and a sub-divider which is connected thereto and which has a fixed integer dividend, the latter sub-divider also constituting a binary-to-digitial converter.

United States Patent Janssen 1 1 Aug. 27, 1974 1 TONE GENERATOR FORGENERATING [56] References Cited SELECTED EREQUENCIES UNITED STATESPATENTS [75] Inventor: Daniel Johannes Gerardus .lanssen, 3,215,86011/1965 Neumann 328/27 X Emmasingel, Eindhoven, 3,500,213 3/1970 Ameau328/27 X Netherlands 3,551,826 12/1970 Sepe 328/25 X 3,657,657 4/1972Jefferson 328/14 1 Asslgneel PhlllpscorporalwmNew 3,752.97; 8/1973 Thornet a1. 32s/14x York, NY. 22 Filed; May 29, 1973 Primary ExaminerJ0hnZazworsky Attorney, Agent, or Firm-Frank R. Trifari [21] Appl. No.:364,969

1 1 ABSTRACT [30] Foreign Apphcatmn Pnomy Data A tone generatorcomprising a pulse oscillator, a di- June 10, 1972 Netherlands 727933Vider having an adjustable integer dividend is connected thereto andwhich comprises a sub-divider U-S. i. having an adjustable fractionaldividend and a ub- 328/27- 307/261 divider which is connected theretoand which has a [5 Cl. fixed integer dividend the latter ub divider alsocon- Fleld of Search l8, a binary to digitial onverter 6 Claims, 13Drawing Figures PULSE GENERATOR 'NTEGER V R [f' m i 1 i 7 10 SELECTIONSWITCHING UNIT INTEGER DIVIDER PATENTED 2 7 I974 3 832 6 39 SHEET 1 7PULSE GENERATOR I INTEGER DIVIDER f 1 5 In M l a SUB-DIVIDERS 1 K) I E iI 1 1 l ln l 12 H9 [INTEGER DIVIDER L ECTIQN SWITCHING Fig.1

1 UNIT CURRENT /5SOURCE 18 A 25 K H U I6 wEf INJECTION LOGIC T ELEMENTELEMENT Fl .2 a F '9 b K OR-GATE AND-GATE H 3-5 7 19 I A B A. B Q" B7D B21 PAIENIEDmczmn SHEET b 0? 7 Fig.5a

TONE GENERATOR FOR GENERATING SELECTED FREQUENCIES The invention relatesto a tone generator for generating a number of selected frequencies,comprising a pulse oscillator, a frequency divider which is connected tothe pulse oscillator and which has an adjustable integer dividend forderiving the selected frequencies from the pulse oscillator frequency,and a binary-to-digital converter for forming approximately sinusoidaldigital signals.

Tone generators of this kind are advantageously used in practice forgenerating frequencies of crystal stability.

Netherlands Patent Application 7.013,78O describes a tone generatorwhich is used in a data modulator and which comprises a pulse sourcehaving a pulse repetition frequency which is equal to a multiple of theselected frequencies to be generated, and from which a pulse sequence isderived, by means of a frequency distribution network, which is appliedto a binary-todigital converter.

Due to the frequency dividing capacity of the binaryto-digitalconverter, the pulse repetition frequency of the pulse source is chosento be higher by a multiplication factor which is equal to the frequencydividing capacity than the smallest common denominator of thefrequencies to be generated. If a very closely approximated sine wave isto be generated, a digital converter having a high frequency dividingcapacity is required.

This has the drawback that an oscillator having a very high oscillationfrequency is to be used. This implies, on the one hand, that the numberof logic elements to be used is large and, on the other hand, that thelogic elements used must be suitable for operation at these very highfrequencies; logic elements are then required which have a comparativelylarge dissipation.

The invention has for its object to realize a tone generator of the kindset forth by means of a comparatively small number of logic elements, inwhich the operating speed of the logic elements can be comparativelylow, and in which the selected frequencies are generated with a closelyapproximated sine wave by means of few additional logic elements.

The device according to the invention is characterized in that thedivider having an integer dividend comprises an adjustable sub-dividerhaving a fractional dividend, a sub-divider having a fixed integerdividend being connected thereto, the latter sub-divider alsoconstituting the binary-to-digital converter.

According to a further characteristic, the integer divider comprises aprogramming network, to which the sub-divider having the adjustablefractional dividend is connected for generating reset signals at givencounting positions of this sub-divider, to which a frequency selectionswitching unit is connected for the selection of some of the generatedreset signals for each selected frequency, and to which the sub-dividerhaving the fixed integer dividend is connected for causing theappearance of the selected reset signals according to a fixed sequenceand for a number of times per cycle of the integer divider whichcorresponds to the dividend of the sub-divider having the fixed integerdividend, the programming network being connected to the subdividerhaving the adjustable fractional dividend forresetting the sub-dividerhaving the adjustable fractional dividend to a starting position by anyrelevant reset signal appearing.

The invention and its advantages will be described with reference to theembodiments shown in the Figures.

FIG. 1 shows an embodiment of a tone generator according to theinvention.

FIGS. 2a to 2d show some injection-logic elements by means of which thetone generator shown in FIG. 1 is realized.

FIG. 3 shows the diagram of a divider which is used in the tonegenerator shown in FIG. 1..

FIGS. 4, a to k, show signals which can occur in the divider shown inFIG. 3.

FIGS. 5a and 51) show parts of a binary-to-digital converter which isused in the tone generator shown in FIG. 1.

FIGS. 6, a to i, and FIG. 7 show signals which can occur in the parts ofa binary-to-digital converter shown in FIGS. 5a and 5b.

FIG. 8 shows the diagram of another divider which is used in the tonegenerator shown in FIG. 1.

FIG. 9 shows an embodiment of a tone pushbutton selection switchingdevice used in the tone generator shown in FIG. 1.

The embodiment shown in FIG. 1 illustrates an application of the tonegenerator according to the invention in a push-button telephone set, thesetbeing adapted to be used in a special tonefrequency signallingsystem. In this signalling system use is made of two different frequencybands which are situated within the frequency band of a speech channel,four selected frequencies which are used as signalling frequencies beingsituated in each frequency" band. For the transfer of information, asignalling frequency of one frequency band is combined with a signallingfrequency of the other frequency band.

In Document No. 10l,C.C.I.T.T. Com. XI recommends 697 Hz, 770 Hz, 852 Hzand 941 Hz successively for the signalling frequencies situated in thelowest of the two frequency bands, and 1,204 Hz, 1,336 Hz, 1,477 Hz and1633 Hz successively for the signalling frequencies situated in thehighest of the two frequency bands.

These frequencies may not deviate more than 1.5 percent, and the levelof the sum of all higher harmonics must be at least 20 dB lower than thelevel of the fundamental wave.

So as to satisfy the i 1.5 percent frequency tolerance requirement,while taking into account ageing phenomena and the effects of variationsof temperature, relative humidity and voltage, the signallingfrequencies are preferably derived from crystal-stabilized oscillators.It is economical to use one crystal-controlled oscillator and to deriveall signalling frequencies from the oscillation frequencies supplied bythis oscillator so that it is at the same time ensured that thesignalling frequencies cannot be shifted with respect to each other.Digital techniques are used to comply with the frequency tolerancerequirement and to enable realization of the tone generator inintegrated form.

Use is made of a pulse oscillator l which is known per se, and thesignalling frequencies are derived from the oscillator frequencysupplied by the pulse oscillator by means of integer dividers.

So as to keep the number of dividers small, dividers are used which havean adjustable integer dividend,

two integer dividers 2 and 3 having an adjustable dividend being usedbecause of the fact that two signal frequencies must be simultaneouslygenerated in the special signalling system. These dividers comprisecontrol terminals 8 and 9 whereto a frequency selection switch- 5 ingunit 12 is connected by means of which the dividends can be adjusted.The oscillator frequency must then be equal to the smallest commondenominator of the signalling frequencies to be generated, the saidsmallest common denominator being very large for the signallingfrequencies recommended by the C.C.I.T.T. Commission. The pulsefrequencies supplied by the dividers 2 and 3 generally contain a highpercentage of higher harminics. So as to satisfy the requirement thatthe level of the sum of all harmonics must be at least 1 dB lower thanthe level of the generated signalling frequency, filters must be used;in view of the fact that it must readily possible to integrate thesefilters, they must be realized in digital form. These digital filtershave a frequency dividing capacity which is proportional to the qualityof these filters. When use is made of such filters, the oscillatorfrequency would normally have to be chosen to be higher by a factorwhich is equal to the frequency dividing capacity than the smallestcommon denominator of the signalling frequencies. This implies that manylogic elements must be used; these elements must have an operating speedwhich is adapted to this high oscillator frequency. Elements of thiskind are uneconomical and have a high dissipation. In that case it isnot possible to use a tone generator of this kind in a push-buttontelephone set.

The invention enables the use of a lower oscillator frequency in thateach of the integer dividers 2 and 3 comprises a sub-divider 4, 6 havingan adjustable fractional dividend, and a sub-divider 5, 7 having a fixedinteger dividend which is connected thereto, the latter sub-divider alsoconstituting the binary-to-digital converter.

A further reduction of the oscillator frequency is obtained by utilizingthe permissible 1.5 percent frequency tolerance by selecting signallingfrequencies which have a comparatively small smallest commondenominator, but which deviate only slightly (less than 1.3/00) from thefrequencies recommended by C.C.I.T.T. Com. XI in Document No. 101.

Consequently, the frequency of the oscillator amounts to 221.8 kHz inthis embodiment. The dividends of the integer dividers 2 and 3 which arerequired so as to derive the desired signalling frequencies therefromare stated, together with these frequencies, in columns 2 and 1,respectively, of table A.

tone generator must be suitable for operation at a supply of 2.7 voltsand a supply current of 10 mA. To this end, all logic circuits arerealized by means of injection logic. This kind of logic is described inthe U.S. Pat. application Ser. No. 253,348, filed on May 15, 1972 andassigned to the same assignee.

The basic element of all injection logic circuits is shown in FIG. 2a,and consists of a multicollector transistor 14 without resistors, forwhich it holds good approximately that the base is connected to a unitcurrent source 15. When input terminal 16 is conductively connected toearth, referred to hereinafter as that a low signal is applied to inputterminal 16, the current of current source 15 will be applied to earth,and the transistor 14 will not be conductive. Any currents applied tothe output terminals 17 and 18 which are connected to the collectorscannot be carried off, which will be referred to hereinafter as that theoutput terminals 17 and 18 supply a high signal. If a high signal isapplied to input terminal 16, the current of current source 15 will flowto earth via the base-emitter junction of transistor 14, and currentsapplied to the output terminals 17 and 18 will flow to earth via thecollector-emitter junction. The output terminals 17 and 18 then supply alow signal. This basic element, operating as an inverter, is denoted bythe symbol shown in FIG. 2b. The direct interconnection of a pluralityof inputs is prohibited in injection logic.

According to this logic system, an AND-gate is realized byinterconnecting two conductors as shown in FIG. 2c. The output terminalsupplies a high signal (cannot take off current) only if A and B arehigh (i.e., no current is derived from A or B). This means that thesignal on the output terminal satisfies the logic relation A. B of thelogic signals A and B applied to the inputs.

FIG. 2d shows an OR-gate which is constructed according to this logicsystem. The logic signals A and B applied to the input terminals areinverted to form A and B by the inverters l9 and 20. Subsequently, thesesignals are combined to form A'B by the AND-gate which is realized bythe interconnected outputs of the inverters l9 and 20, and this signalis converted to the output signal A B by way of inverter 21.

By means of the inverter, the AND-gate and the OR- gate shown in theFIGS. 2b to 2d, all more complex logic elements such as bistableelements, can be realized in known manner. Each of the bistable elementsused in the circuit comprises a set input S, a trigger The logic usedwill be considered before a detailed description is given of the tonegenerator.

The use of the tone generator in a push-button telephone set in thepresent embodiment implies that the input T, a condition input D, asignal output Q, and an inverted signal output 6. A high signal which isapplied to the set input S sets the element to the set state which ischaracterized in that the signal output 0 supplies a high signal. A highor a low signal applied to the condition input D can set or reset.respectively, the bistable element at the instant at which a signalapplied to the trigger input T changes'from high to low. A two-divideris obtained in known manner by connecting the inverted signal output 6of a bistable element to the condition input D.

FIG. 3 is a detailed representation of the divider 2 having anadjustable integer dividend according to the invention. The sub-divider4 comprises four cascadeconnected bistable elements 22 to 25 which areconstructed as two dividers. The trigger input T of element 22 isconnected to the output terminal 13 of the pulse oscillator 1 which isnot shown in this Figure, and the trigger inputs T of the elements 23 to25 are connected to the signal outputs Q of the preceding elements 22 to24. The pulse sequence which is applied to terminal 13 by the oscillatoris shown in FIG. 4a. The signals which are successively derivedtherefrom by two-division by the elements 22 to 25 are shown in the FIG.4, b to e.

The sub-divider 5, having a fixed dividend, is connected to thesub-divider 4 having an adjustable dividend. The fixed dividend of thissub-divider 5 is chosen to be equal to twelve in this embodiment. So asto realize this dividend, sub-divider 5 comprises four bistable elements26, 27, 28 and 29 which are interconnected as described hereinafter, theelements 26 and 29 thereof being connected as two-dividers. Because theinputs of elements which are constructed according to injection logicmay not be directly interconnected, the inverters 30 to 34 are used soas to obtain a plurality of identical outputs to which inputs can beindividually connected, these inverters being connected to the signaloutput Q or the inverted signal output 6 of the bistable elements 25, 26and 27 supplying the inverted signals with respect to the desiredsignals. For example, the inverter 30 is connected to the invertedsignal output 6 of element 25 so as to supply the trigger inputs T ofthe elements 26, 27 and 28, connected to the outputs of the inverter 30,with a signal which is identical to the signal supplied by the signaloutput Q of element 25.

Furthermore, so as to obtain a signal for the condition input D ofelement 27 such that the elements 26, 27 and 28 constitute asix-divider, the inverters 35, 36 and 37 are provided. Inverter 35 isconnected to the inverters 32 and 33 so as to supply on its output thelogic OR-function of the logic signal values applied to the inverters 32and 33. Similarly, inverter 36 is connected to the inverters 31 and 34so as to supply on its output the logic OR-function of the logic signalvalues applied to the inverters 31 and 34. The inverter 37 is connectedto the output of the inverter 35 and to the inverted signal output 6 ofbistable element 28 so as to supply on its output the logicNAND-function of the logic signals applied to its input, the outputs ofthe inverters 36 and 37 being connected to the condition input D ofelement 27 so as to apply thereto the logic AND-function of the signalssupplied by the inverters 36 and 37. Furthermore, the signal output ofelement 27 is connected, via inverter 34, to the condition input D ofelement 28.

The operation of the sub-divider will be described with reference to theFIG. 4, f to j, assuming that the bistable elements 26 to 29 are in theset state; the output signal of sub-divider 4 which is shown in FIG. 4eis shown again at a reduced time scale in FIG. 4f.

Because the elements 26 to 28 are in the set state, the inverter 35causes inverter 36 and the inverter 37 to supply a high signal, with theresult that a high signal is also applied to the condition input D ofelement 27.

As a result of the negative edge appearing at the instant t (FIG. 4f),element 26 is reset, element 27 remains set and element 28 is reset asis shown in the FIG. 4, g, h and i. The resetting of the element 26causes the output signal of inverter 35 to change from high to low, withthe result that for the time being the resetting of element 28 does notinfluence the high output signal supplied by the inverter 37. Thenegative edge which appears at the instant t sets element 26 to the setstate, with the result that the output signal of inverter 35 becomeshigh again. In conjunction with the high signal supplied by the invertedsignal output 6 of element 28, this high output signal causes the outputsignal of inverter 37 to change from high to low with the result that alow signal is applied to the condition input D of element 27.Consequently, the negative edge occurring at the instant t will resetboth the element 26 and the element 27. Because elements 26 and 27 aresimultaneously reset, the value of the signals supplied by the inverters35 and 36 is not changed. Only the signal applied to the condition inputD of element 28 changes from low to high. The negative edge appearing atthe instant t will consequently, set elements 26 and 28. Because element26 is set, the output signal of inverter 36 changes from high to low,with the result that the signal applied to the condition input D ofelement 27 remains low, even though the output signal of inverter 37 hasbecome high due to the setting of element 28. The negative edgeappearing at the instant t resets element 26, with the result that thesignal supplied by inverter 36 becomes high and a high signal is appliedto condition input D of element 27. The negative edge which appears atthe instant t sets element 26 and element 27. All three elements 26, 27and 28 are then set, so that as from the instant t the cycle of thesuccessive states of the said elements is repeated. The pulse sequencesupplied by element 28, consequently, has a pulse repetition frequencywhich is six times smaller than the pulse repetition frequency of thepulse sequence supplied by the sub-divider 4. Because the trigger inputT of the bistable element 29 which is connected as a twodivider isconnected to the signal output Q of element 28, the pulse repetitionfrequency of the pulse sequence supplied by element 29 is twelve timessmaller than the pulse repetition frequency of the pulse sequencessupplied by the sub-divider 4 as shown in FIG. 4j.

So as to obtain a digital signal which is approximately sinusoidal, thesub-divider 5 comprises a weighting network 38 to which the inverters 32and 34 and the inverted signal output Q of element 29 are connected. Theweighting network 38 comprises a gate circuit as shown in FIG. 5a inorder to form signals which determine the phases of the approximatedsine wave, and a current source circuit as shown in FIG. 5b which isconnected thereto and by means of which the amplitudes of theapproximated sine wave are determined.

The signals supplied by the inverters 32, 34 and the inverted signaloutput Q of element 29 are applied to the input terminals 40, 41 and 42of the gate circuit shown in FIG. a, the said signals being shown inFIGS. 6a, 6b and 66.

Connected to these input terminals are the inverters 43, 44 and 45 so asto have a plurality of identical signal outputs available for each inputterminal in order to prevent inputs ofinverters which are connectedthereto from being directly connected to each other. The signals appliedto the input terminals 40, 41 and 42 are recovered from the signalssupplied by the inverters 43, 44 and 45 by means of the inverters 46, 47and 48.

Because the outputs of the inverters 43, 4'7 and 48 are interconnected,the logic AND-function of the inverted signal of the input signal shownin FIG. 6a and the input signals shown in the FIGS. 6a and 6c are ob'tained on inverter 50, the said signal being shown in FIG. 6d. Aftersuccessive inversion by the inverters 50 and 53, this signal is appliedto output terminal 53-1 in unmodified form.

Because the outputs of the inverters 47 and 48 are interconnected, thelogic AND-function of the input signals shown in the FIGS. 6!; and 6c isapplied to inverter 51, the said signal being shown in FIG. 6e and beingapplied in unmodified form to the output terminals 54-3 after successiveinversion by the inverters 51 and 54.

The inverter 49 constitutes an OR-gate, in conjunction with theinverters 44 and 46 which are connected to the input of this inverter,with the result that this inverter forms on both its outputs the logicORfunction of the input signal shown in FIG. 6a and a signal which isobtained by inversion of the input signal shown in FIG. 6b. A firstoutput of inverter 49 is connected, together with an output of inverter48, to the input of inverter 52 in order to supply this inverter withthe logic AND-function of the signal supplied by inverter 49 and theinput signal shown in FIG. 60. This signal, shown in FIG. 6f, is appliedin unmodified form to the output terminal 55-4 after successiveinversion by the inverters 52 and 55.

A second input of inverter 49 is connected, together with an output ofinverter 45, to inverter 56 in order to supply the output terminals 56-4with the inverted logic AND-function of the signal supplied by inverter49 and a signal which is derived from the input signal shown in FIG. 6cby inversion. The signal applied to the output terminals 56-4 is shownin FIG. 6g.

The output of inverter 47 is connected, together with the output ofinverter 45, to an inverter 57 in order to supply the output terminals57-3 with the inverted logic AND-function of the input signal 6b and asignal which is obtained from the input signal shown in FIG. 60 byinversion. This signal is shown in FIG. 6h. Furthermore, the outputs ofthe inverters 43, 45 and 47 are connected to an inverter 58 in order tocause the inverter 58 to supply the inverted logic AND-function ofsignals which are derived from the input signals shown in FIGS. 6a and60 by inversion and the input signal shown in FIG. 6b, the said signalbeing shown in FIG. 6i.

As appears from the FIGS. 6d and 6i, the inverters 53 to 58 supplypulses which are symmetrically arranged with respect to each other,which have the same pulse repetition frequencies, and which have adifferent pulse duration, with respect to each other, the duration ofthe pulses being odd multiples of approximately one twelfth of the pulseperiod of the pulse sequence supplied by subdivider 5. Consequently, ineach period of the pulse sequence supplied by the sub-divider 5 twelvephases are characterized which are approximately regularly distributedover 360C.

In order to obtain an approximately sinusoidal amplitude which changesat these phase instants, the inverters 53, 54, 55, 56, 57 and 58 areprovided with one output terminal 53-1, three output terminals 54-3,four output terminals 55-4, four output terminals 56-4, three outputterminals 57-3, and one output terminal 58-1, respectively, which areconnected to the current source circuit shown in FIG. 5b. This circuitcomprises 16 parallel-connected current sources, divided in six groupsof one, three, four, four, three and one current source, respectively,which are denoted by 59; 68-62; 63-66; 67-71; 72-75 and 76,respectively. Only one current source is shown of each group. Eachcurrent source comprises a first transistor 59-1, 60-1, 76-1, and asecond transistor 59-2, 60-2, 76-2, which is connected in seriestherewith. All current sources are connected between the terminals 78and 79 of a supply voltage source not shown, in series with a resistor77. Also provided between these terminals is a voltage divider which iscomposed of the resistors 80 and 81, the centre tapping of the saidvoltage divider being connected to the bases of all transistors 59-1,59-2, 76-1, 76-2. The voltage of the centre tapping of the voltagedivider 80, 81 is selected such that all transistors 59-1 to 76-1 carryan identical, constant current. The output terminals 53-1 to 58-1 of thegate circuit are connected, via input terminals 59-3 to 76-3, toconnections which are provided between the collectors of the transistors59-1, 60-1, 76-1 and the emitters of the transistors 59-2, 60-2, 76-2.If the signal applied to an input terminal, for example, 59-3, is high,the current flows from the main current path of transistor 59-1 to earthvia the main current path of the transistor 59-2 and resistor 77. Thiscurrent then causes a voltage drop across resistor 77. If the signalapplied to the input terminal 59-3 is low, the current flows from themain current path of transistor 59-1, via input terminal 59-1 and theinverter 59 which is connected thereto, to earth with the result thatthis current cannot contribute to the voltage across resistor 77.Because the inverters 53 to 58 control one, three, four, four, three,and one current source, respectively, by means of the signals shown inthe FIGS. 6d to 6i, the sinusoidal voltage signal shown in FIG. 7 isformed across resistor 77, the said sinusoidal voltage signal comprisingonly the (n-12) +first harmonics (n l, 2, 3,

By connecting a capacitor 83 parallel to resistor 77, a low-pass filteris obtained which suppresses the har monies, with the result that theC.C.I.T.T. requirement as regards the level of these harmonics issatisfied. The sinusoidal voltage signal is available between theterminals 82 and 79 which constitute the output terminal 10 shown in theFIGS. 1 and 3.

For generating the four signal frequencies which are situated in thehigh frequency band, it must be possible to adjust the dividends ofdivider 2 which are shown at these frequencies in Table A, column 2,under the control of the signals which are applied to the control input8 by the frequency selection switching unit 12. Because the dividend ofsub-divider 5 is equal to twelve, the dividend of sub-divider 4 must beadjusted to the first four values shown in column 3 of Table A for thesignalling frequencies which are situated in the high frequency band. Tothis end. sub-divider 4 is provided with the programming network 84which is shown in FIG. 3. This programming network comprises theconductors 85 to 91 which are connected, via the OR-gate 100 which isformed by the inverters 92/98 which are connected to these conductorsand the inverter 99 which is connected thereto, to an inverter 101,together with the input terminal 13. This inverter 101 is connected, viaan inverter 102, to the set inputs S of the bistable elements 22, 23 and24. By means of this programming network 84 a reset signal can bederived at the instants at which the sub-divider 4 is in one of thecounting positions 11 to 16, the said reset signal being used to resetthe sub-divider 4 to a starting position which is defined by the setstate of the elements 22 to 25.

To this end, the inverted signal outputs of the elements 22, 23 and 24are connected to inputs of inverters 103, 104 and 105, the outputs ofthe inverter 103 being connected to the conductors 86, 87 and 90, theoutputs of the inverter 104 being connected to the conductors 85, 86, 87and 91, the outputs of inverter 105 being connected to the conductors88, 89, 90 and 91, and the signal output Q of element 25 being connectedto the output of OR-gate 100, each connection point constituting anAND-gate. When the signal on input 13 is high, the reset signal isobtained if one of the conductors 85 to 91 supplies a high signal viaOR-gate 100 and the signal output Q of element 25 also supplies a highsignal. If it is assumed that sub-divider 4 is in its starting position,the signal output Q of element 25 becomes high (FIG. 4e) after ninepulses have been applied to the input terminal; the way in which thesub-divider 4 is connected to the programming network then causes, asshown in FIG. 4, b and c, all signals applied by subdivider 4 to theconductor 85 to be high for the eleventh pulse applied to sub-divider 4,the signals applied to conductors 86 and 87 to be high for the twelfthpulse applied to sub-divider 4, the signals applied to the conductors 88and 89 to be high for the thirteenth pulse applied to sub-divider 4, thesignals applied to conductor 90 to be high for the fourteenth pulseapplied to sub-divider 4, and the signals applied to conductor 91 to behigh for the fifteenth pulse applied to the sub-divider 4, all elements22 to 25 of sub-divider 4 being set by the sixteenth pulse because thesubdivider 4 has the completed one counting cycle.

So as to obtain the fractional dividend of the subdivider 4 which isrequired for a given signal frequency, control signals are generatedunder the control of the frequency selection switching unit 12 in amanner which will yet be described, the said control signals serving toselect two of the eight reset signals which are generated at givencounting position of the sub-divider 4, these selected reset signalsbeing arranged, under the control of signals supplied by sub-divider 5,such that they alternately occur in a given time sequence.

To this end, the programming network 84 is provided with input terminals8-1 and 8-2 to which inverters 106 and 107 are connected. The frequencyselection switching unit 12 is connected to these input terminals 8-1and 8-2 which constitute the control terminal 8 shown in FIG. 1. Thisdevice 12 supplies two logic signals to the input terminals 106 and 107when a button is depressed in a manner which will yet be described. Bymeans of these two logic signals, four signal states can bedistinguished, each signal state being used to select two of theeight-reset signals. This is achieved in that the conductors and 86connected to outputs of inverter 106 as well as to outputs of inverter107, the conductors 87 and 88 being connected to outputs of the inverter106, and the conductors 89 and 90 being connected to the outputs of theinverter 107.

If the signals applied to the input terminals 8-1 and 8-2 are both low.the inverters 106 and 107 supply high signals. The conductor whichreceives only high signals from sub-divider 4 at a given countingposition then applies a high signal via OR-gate which, in conjunctionwith the high state of the signal output Q of element 25, is capable ofresetting sub-divider 4. This occurs first for the conductor 85 at thecounting position eleven. By keeping the signal which appears incounting position 11 on conductor 85 low in the manner yet to bedescribed, the signal on conductor 86 becomes high at counting positiontwelve of the sub-divider 4, the said signal then being capable ofresetting the subdivider 4. When a low signal is applied to both inputterminals 8-1 and 8-2, the reset signals which are generated at thecounting positions 11 and 12 are thus selected.

If the signal which is applied to input terminal 8-1 is low and thesignal which is applied to input terminal 82 is high, a high signal isapplied only to the conductors 87 and 88. The low signal which isapplied to the conductors 85 and 86 keeps the signals appearing on theseconductors low due to the connection points of the outputs of theinverters 103, 104 and 105 which act as AND-gates. As a result, thereset signals which are derived at the counting positions twelve andthirteen are selected.

If the signal applied to input terminal 8-1 is high and the signalapplied to input terminal 8-2 is low, the inverter 107 applies a highsignal only to the conductors 89 and 90. The reset signals which arederived at the counting positions thirteen and fourteen are thenselected.

If the signals applied to both input terminals 8-1 and 8-2 are high, alow signal is applied to the conductors 85 to 90. Only the reset signalderived from the counting position 15 and the signal which causes theresetting to the starting position in the counting position 16 ofsub-divider 4 are then selected.

The sequence in which the two reset signals which are selected under thecontrol of the frequency selection switching unit 12 succeed each otheris determined by subdivider 5. The outputs of the inverters 31 and 33 ofthis sub-divider are connected to an inverter 108, the outputs of whichare connected to the conductors 85 and 91, an output of inverter 31being connected to conductor 87, and a further output being connected toconductor 89, an output for inverter 34 also being connected to thelatter conductor. The operation will be described in detail withreference to the signals shown in the FIG. 4, a to k.

As already described, each pulse supplied by subdivider 4 (FIG. 4f)changes the state of the elements 26 and 27 in accordance with thesignals shown in FIG. 4, g and h. These figures show that the signalsapplied to inverter 108 are both high during the time intervals situatedbetween the instants t t t t t t and r r,,. The signal supplied byinverter 108 is low during these intervals. If the signals applied toboth input terminals 8-1 and 8.2 are low for the time intervals duringwhich inverter 108 applies a high signal to conductor 85, this conductor85 will carry a high signal at the counting position 11, and during thetime intervals in which invcrtcr 108 supplies a low signal to conductor85, the conductor 86 will carry a high signal at the counting position12. The counting positions of the sub-divider 4 change at the instantsat which the trailing edges of the pulses applied to input terminal 13appear, so that a signal supplied via OR-gate 100 by the conductor 85 or86, changes from high to low at the instants of appearance of theeleventh or the twelfth counting position. respectively. The signalapplied from input terminal 13 to inverter 101, however, is then low.The signal applied to input terminal 13 becomes high after one halfpulse repetition time of the pulse sequence applied to input terminal13, with the result that via the inverters 101 and 102 a high signal(shown in FIG. 4k) is applied to the set inputs S of the elements 22, 23and 24. This signal resets the sub-divider 4 to its starting positron.

As appears from FIG. 4, g, h, k and a, assuming that sub-divider 4 is inthe starting position, this sub-divider is reset only after 11 pulseshave been received on input terminal 13, subsequently after 12 and afterthat, as appears from FIG. 4, g and h, successively after 11, ll,11,12,11, 12,11, 11, 11 and 12 pulses have been received on inputterminal 13 in each cycle of the subdivider 5. Because the cycle ofsubdivider 5 is equal to the cycle of divider 2, the dividend of thisdivider is 136, the said dividend deriving, according to Table A, thesignal frequency 1,633 Hz from a generator frequency of 221.8 kHz. Themean dividend of subdivider over a cycle of divider 2 is 34/3, as isindicated in Table A, column 3. Because the sub-divider 4 is not alwaysreset at the same counting position, the instants I, to I as shown inFIG. 4 are not regularly distributed. These instants are also shown inFIG. 6 and FIG. 7. The sequence of appearance of the instants, however,is chosen such that the approximated sine wave is mirrorsymmetrical,with the result that no even harmonics are generated. The increase ofthe number and the intensity of the odd higher harmonics caused by theirregular time distribution is so small that the requirements imposed byC.C.I.T.T. are readily satisfied.

The signal which is applied by inverter 31 to the conductor 87corresponds to the signal shown in FIG. 4g. This means that, if a lowsignal is applied to input terminal 8-1 and a high signal is applied toinput terminal 8-2, the conductors 88 and 87 alternately carry a highsignal at the counting positions 13 and 12, respectively, of thesub-divider 4, thus resetting the sub-divider. The mean dividend ofsub-divider 4 is then equal to 25/2, with the result that the dividendof divider 2 is equal to 150. According to Table A, a signal having afrequency of 1,477 Hz is then generated.

The signals applied by the inverters 31 and 34 to conductor 89correspond to the signal shown in FIG. 4g, and to a signal which isobtained by inversion of the signal shown in FIG. 4/1. This means that ahigh signal is applied to conductor 88 only during the intervalssituated between the instants t t and I t,,. If a high signal is appliedto input terminal 8-1 and a low signal is applied to input terminal 8-2,the sub-divider 4 is reset, because the conductors 90 and 91 carry highsignals in the described manner, successively after 14, 14, 14, l3, 14,14; 14, 14, 14, 13, 14 and 14 pulses have been received on inputterminal 13 in each cycle of divider 2. The mean dividend of subdivider4 is then equal to 83/6, so that the dividend of divider 2 is equal to166.

According to Table A, a signal having a frequency of 1.336 H7. is thengenerated.

The signal which is applied by inverter 108 to conductor is also appliedto conductor 91. If high signals are applied to both input terminals 8-1and 8-2, the conductor will carry a high signal, if inverter 108supplies a high signal, after 15 pulses have been applied to inputterminal 13, the said signal resetting the subdivider 4 and, if inverter108 supplies a low signal, the sub-divider 4 will have returned to itsstarting position after 16 pulses have been received on input terminal13. It is thus achieved that in each cycle of the divider 2 thesub-divider 4 is successively reset after 15, 16, 15, 15, 15, 16; 15,16, 15, 15, 15 and 16 pulses have been applied to input terminal 13. Themean dividend of sub-divider 4 is then equal to 46/3, and the dividendof divider 2 is then equal to 184. In accordance with Table A, a signalhaving a frequency of 1,204 Hz is then supplied.

The sequence of the counting positions at which the sub-divider 4 issuccessively reset is also chosen for the generated signallingfrequencies of 1,477 Hz, 1,336 Hz and 1,204 Hz such that theapproximated sine wave is mirror-symmetrical so that no even harmonicsare generated.

The frequencies which are situated in the low frequency band of thespecial signalling system are derived from the oscillator frequency bymeans of the integer divider 3 which is composed, in accordance with theinvention, of a sub-divider 6 having a fractional, adjustable dividend,and a sub-divider 7 having a fixed, integer dividend. This divider 3 isshown in detail in FIG. 8. As appears from Table A, the dividends whichhave to be realized by means of this divider are larger than those ofdivider 2. Consequently, the divider 3 shown in FIG. 8 differs from thedivider 2 shown in FIG. 3, on the one hand, in that between the bistableelements 24 and 25 a bistable element 109 is provided whose set input Sis connected to an output of inverter 102, the trigger input T beingconnected to signal output Q of element 24, the signal output 0 beingconnected to the trigger input T of element 25, and the inverted signaloutput 6 being connected to an additionally provided inverter 110 and,on the other hand, in that the sub-dividers 6 and 7 are connected to theconductors 85 to 91 in a manner other than the subdividers 4 and 5,conductor not being connected to an output of inverter 107. Disregardingthe fact that the input terminals are denoted by 9-1 and 9-2 inaccordance with the control terminal 9 shown in FIG. 1 and the fact thatthe output terminal as shown in FIG. 1 is denoted by 1 1, the otherparts are denoted by the same references as used for the divider 2.

Besides the fact that the signal output Q of element 25 supplies a highsignal in the counting positions 16 to 32, inverter 104 supplies a highsignal to conductor 85 only if sub-divider 6 is in counting position 19,high signals being applied by the inverters 103 and 104 to conductor 86when the sub-divider 6 is in counting position 20, high signals beingapplied to conductor 87 by inverters 103 and when sub-divider 6 is incounting position 21, a high signal being applied to conductor 88 by theinverter 105 when subdivider 6 is in counting position 22, high signalsbeing applied to conductor 89 by the inverters 103, 104 and 105 whensub-divider 6 is in counting position 24, high signals being applied toconductor 90 by the inverters 103 and when subscribed, i.e., if thesignals applied to both input terminals are low, the conductors 85 and86 are selected, the conductors 87 and 88 being selected if the signalapplied to input terminal 9-1 is low and the signal applied to inputterminal 9-2 is high, the conductor 89 being selected if the signalapplied to input terminal 9-1 is high and the signal applied to inputterminal 9-2 is low, and the conductors 90 and 91 being selected if thesignals applied to the two input terminals 9-1 and 9-2 are high. Thesequence in which the conductors 85, 86; 87, 88 and 90, 91, which areselected per pair, supply reset signals is determined in that theconductors 85 and 87 are connected to the outputs of the inverters 31and 33, and in that conductor 90 is connected to an output of inverter31. As appears from the FIG. 4, g and h, the inverters 31 and 33 supplyhigh signals only during the time intervals which are situated betweenthe instants r r 2 i t t t and t so that when conductor pair 85, 86 isselected, the subdivider 6 is reset after 20, 19, 20,20, 20, 19; 20, 19,20, 20, 20 and 19 pulses have been successively received on outputterminal 13 in each cycle of divider 3. The mean dividend of subdivider6 then amounts to 59/3, and the dividend of divider 3 is 236. Inaccordance with Table A, a frequency of 941 Hz is then supplied tooutput 11.

Similarly, when the conductor pair 87 and 88 is selected, thesub-divider 6 is reset after 22, 21, 22, 22, 22, 21; 22, 21, 22, 22, 22and 21 pulses have been successively received on input terminal 13 ineach cycle of divider 3. The mean dividend of sub-divider 6 is then68/3, and the dividend of divider 3 is equal to 260, the said dividendcorresponding according to Table A to a signal frequency of 852 HZ whichis applied to output terminal 11.

When conductor 89 is selected sub-divider 6 is reset after every 24pulses received on input terminal 13. The dividend of divider 3 is then288, which corresponds according to Table A to a signal frequency of 770Hz for the signal applied to input terminal 11.

The inverter 31 applies the signal shown in FIG. 4g to conductor 90,with the result that upon selection of the conductor pair 90, 91 thesub-divider 6 is reset after 27 and 26 pulses have alternately beenreceived on input terminal 13. The dividend of sub-divider 6 is thenequal to 53/2, and the dividend of divider 3 then amounts to 318, whichaccording to Table A makes the signalling frequency of the signalappearing on output terminal 11 equal to 691 Hz.

The stated sequence of the counting positions at which the sub-divider 6is successively reset in again chosen such that the approximated sinewave is mirrorsymmetrical.

The frequency selection switching unit 12 which supplies the requiredlogic signals to the input terminals 8-1, 8-2 and 9-1, 9-2 is shown inFIG. 9. This device comprises a counter 138 which is composed of fourcascade-connected bistable elements 111, 112, 113 and 114. The outputterminal 13 of the pulse oscillator 1 applies, via the inverter 137,pulses to the trigger inputs T of the bistable elements 111 to 114. As aresult, the counter 138 continuously passes through all successivccounting positions. Also provided is a push-button switch 127 which iscomposed of two pairs of four conductors 127-1 to 127-4 and 127-5 to127-8 which cross each other at right angles. Above each crosspoint (16in total) of the conductor a push-button (not shown) is provided, thesaid push-button pressing, when depressed, the conductors, whichnormally cross each other at the crosspoint against each other, with theresult that they are conductively connected to each other. The invertedsignal outputs 6 of the elements 111 and 112 are coupled, via an OR-gatewhich is formed by the inverters 115, 117 and 123, to the conductor127-5, which the result that only this conductor receives a low signalwhen the elements 111 and 112 are in the set state. The signal output Qof element 111 and the inverted signal output 6 of element 112 arecoupled, via the OR-gate formed by the inverters 116, 117 and 124, toconductor 127-6 with the result that this conductor receives a lowsignal only when element 111 is in the reset state and element 112 is inthe set state. i

The inverted signal output 6 of element 111 and the signal output Q ofelement 112 are coupled, via the OR-gate formed by the inverters 115,118 and 125, to conductor 127-7 so that only this conductor receives alow signal when the element 11 1 is in the set state and element 112 isin the reset state. Furthermore, the signal outputs Q of the elements111 and 112 are coupled, via an ORgate which is formed by the inverters116, 1 18 and 126, to conductor 127-8 so that only this conductorreceives a low signal when the elements 111 and 112 are both in thereset state. During the counting of counter 138, low signals aresuccessively applied to the conductors 127-5 to 127-8, the said lowsignals corresponding to the four possible set/reset state combinationsof the elements 111 and 112.

The conductors 127-1 to 127-4 are connected to inverters 128 to 131.Because these conductors are normally not connected to earth, highsignals are applied to the inverters 128 to 131, with the result thatthe latter supply low signals. When a button is depressed, one of theconductors 127-5 to 127-8 is connected to one of the conductors 127-1 to127-4. The inverter (128 to 131) which is connected to this oneconductor (127-1 to 127-4) supplies a high signal at the instant atwhich the conductor which is connected to the said one conductorsupplies a low signal.

The output of inverter 131 is connected to an inverter 132, togetherwith outputs of the inverters 119 and 1 21 which are connected to theinverted signal outputs Q of the elements 113 and 114. The inverter 132supplies a low signal only if inverter 131 supplies a high signal andthe elements 113 and 114 are both in the set state. The output ofinverter 130 is connected to the input of an inverter 133, together withthe output of inverter 121 and the output of an inverter which isconnected to the signal output Q of element 113. The inverter 133supplies a low signal only if inverter supplies a high signal, theelement 113 is in the reset state, and the element 114 is in the setstate. The inverter 129 is connected to an inverter 134, together withthe output of inverter 119 and an output of an inverter 122 which isconnected to the signal output Q of element 114. This inverter 134supplies a low signal only if inverter 129 supplies a high signal andthe element 113 is in the set state and the element 114 is in the resetstate. The inverter 128 is connected to an inverter 135, together withoutputs of the inverters 120 and 122, the said inverter 135 supplying alow signal only if inverter 128 supplies a high signal and the elements113 and 114 are both in the reset state. During the counting, theelements 113 and 114 apply high signals to the inputs of the inverters132 to 135, the said signals corresponding to the four possibleset/reset state combinations of these elements. The inverters 132 to 135are connected, via an AND-gate by the junction 136, to the input ofinverter 137. It is thus achieved that when a button is depressed, theAND- gate 136 supplies a low signal for only one counting position ofcounter 138 which is characteristic for the button. This low signal isapplied to inverter 137, with the result that the pulses which aresupplied via the oscillator output terminal 13 are blocked. The counter138 remains in the selected counting position as long as the button isdepressed. The output terminals 141-1 and 141-2, connected to theoutputs of the inverters 120 and 122, supply the signals which arerequired for the input terminals 8-1 and 8-2 of divider 2. Similarly,the output terminals 142-1 and 142-2, connected tothe outputs of theinverters 116 and 118, supply the signals required for the inputterminals 9-1 and 9-2. When the button is released, the signal suppliedby AND-gate 136 becomes high again and the counter 138 continuouslycounts the pulses again supplied by the pulse oscillator 1. It will beobvious from the foregoing that, when a button is depressed, two signalfrequencies of the special signalling system are generated, onesignalling frequency being situated in each of the two frequency bands.The frequencies which are selected by depression of a push-button switch127 are shown on the ends of the conductors in FIG. 9 which areinterconnected by the button.

What is claimed is:

1. A tone generator for generating a number of selected frequencies,comprising a pulse oscillator, a frequency divider which is connected tothe pulse oscillator and which has an adjustable integer dividend forderiving the selected frequencies from the pulse oscillator frequency,and a binary-to-digital converter for forming approximately sinusoidaldigital signals, characterized in that the divider having an integerdividend comprises a sub-divider having an adjustable fractionaldividend and a sub-divider having a fixed integer dividend which isconnected thereto, the latter sub-divider also constituting thebinary-to-digital converter.

2. A tone generator as claimed in claim 1, characterized in that theinteger divider is provided with a programming network to which thesub-divider having the adjustable fractional dividend is connected inorder to generate reset signals at given counting positions of thissub-divider, to which a frequency selection switching unit is connectedfor the selection of some of the genrated reset signals for eachselected frequency, and to which the sub-divider having the fixedinteger dividend is connected for causing the appearance of the selectedreset signals according to a fixed sequence and for a number of timesper cycle of the integer divider which corresponds to the dividend ofthe sub-divider having the fixed integer dividend, the programmingnetwork being connected to the sub-divider having the adjustablefractional dividend in order to reset the subdivider having theadjustable fractional dividend to its starting position by any relevantreset signal appearing.

3. A tone generator as claimed in claim 2, characterized in that thereset signals which are selected by the switching unit are derived fromdirectly successive counting positions of the adjustable sub-divider,the sequence in which the selected reset signals appear being selectedsuch that the approximated sine wave is mirror-symmetrical.

4. A tone generator as claimed in claim 1, characterized in that thebinary-to-digital converter comprises a weighting device including aplurality of parallelconnected current sources which are connected inseries with a resistor, and means for successively switching on underthe control of signals derived from the counting positions of the fixedsub-divider, a varying number of said current sources in such a manneras to produce an approximated sine wave across the resistor.

5. A tone generator as claimed in claim 1, characterized in that twoadjustable dividers having an integer dividend are connected to thepulse oscillator, the said dividers being provided with controlterminals to which a frequency selection switching unit is connected.

6. A tone generator as claimed in claim 5, wherein the dividend of oneof the adjustable integer dividers is adjustable under the control ofthe frequency selection switching unit to produce a set of values whichare below the frequency value of the pulse oscillator, the dividend ofthe other adjustable integer divider being adjustable under the controlof the frequency selection switching unit to produce a set of valueswhich are above the value of the oscillator frequency.

$3 33 I UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent Mi.3 832 ,639 Dated ugust 27, 1974 Invented DANIEL J. G. JANSSEN It iscertified that error appears in the above-identified patent and that:said Letters Patent are hereby corrected as shown below:

On the title page, Section [30] change 727933" Signed and sealed this7th day ofjanuary I975.

(SEAL) Attest;

McCOY N. GIBSON JR. '0. MARSHALL DANN Attesting Officer Commissioner ofPatents

1. A tone generator for generating a number of selected frequencies,comprising a pulse oscillator, a frequency divider which is connected tothe pulse oscillator and which has an adjustable integer dividend forderiving the selected frequencies from the pulse oscillator frequency,and a binary-to-digital converter for forming approximately sinusoidaldigital signals, characterized in that the divider having an integerdividend comprises a sub-divider having an adjustable fractionaldividend and a sub-divider having a fixed integer dividend which isconnected thereto, the latter sub-divider also constituting thebinary-to-digital converter.
 2. A tone generator as claimed in claim 1,characterized in that the integer divider is provided with a programmingnetwork to which the sub-divider having the adjustable fractionaldividend is connected in order to generate reset signals at givencounting positions of this sub-divider, to which a frequency selectionswitching unit is connected for the selection of some of the genratedreset signals for each selected frequency, and to which the sub-dividerhaving the fixed integer dividend is connected for causing theappearance of the selected reset signals according to a fixed sequenceand for a number of times per cycle of the integer divider whichcorresponds to the dividend of the sub-divider having the fixed integerdividend, the programming network being connected to the sub-dividerhaving the adjustable fractional dividend in order to reset thesub-divider having the adjustable fractional dividend to its startingposition by any relevant reset signal appearing.
 3. A tone generator asclaimed in claim 2, characterized in that the reset signals which areselected by the switching unit are derived from directly successivecounting positions of the adjustable sub-divider, the sequence in whichthe selected reset signals appear being selected such that theapproximated sine wave is mirror-symmetrical.
 4. A tone generator asclaimed in claim 1, characterized in that the binary-to-digitalconverter comprises a weighting device including a plurality ofparallel-connected current sources which are connected in series with aresistor, and means for successively switching on under the control ofsignals derived from the counting positions of the fixed sub-divider, avarying number of said current sources in such a manner as to produce anapproximated sine wave across the resistor.
 5. A tone generator asclaimed in claim 1, characterized in that two adjustable dividers havingan integer dividend are connected to the pulse oscillator, the saiddividers being provided with control terminals to which a frequencyselection switching unit is connected.
 6. A tone generator as claimed inclaim 5, wherein the dividend of one of the adjustable integer dividersis adjustable under the control of the frequency selection switchingunit to produce a set of values which are below the frequency value ofthe pulse oscillator, the dividend of the other adjustable integerdivider being adjustable under the control of the frequency selectionswitching unit to produce a set of values which are above the value ofthe oscillator frequency.